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The last time semiconductor manufacturer Intel announced a completely new mainstream desktop mainboard core logic set was in April of 1998 with the 100MHz capable 440BX.

Almost a year later to the day, Intel has made another impressive product announcement and has released information on their replacement for the 440EX, 440ZX and 440LX mainboard options at the low end of the mainboard market segment. Named the 810, the new core logic set is the first of three chipsets that will define the direction Intel takes throughout 1999 and well into the year 2000.

Today Sharky Extreme takes a look at the 810, and breaks down the technology behind the new part to help readers determine if the 810 offers enough of an enticement towards upgrading to a Socket370 Celeron based system.

Being the first in a series of three mainboard core logic sets, the Intel 810 occupies the value segment of the new lineup. Later in the year, the 810e, and 820 chipsets will debut from Intel, both heralding the introduction of more advanced versions of the 810 geared towards the middle and high-end of the market segment, including Slot-1 machines.

The 810e will specifically add an integrated version of Intel's newest graphics accelerator (named i752) to the 810's basic i740 graphics powerplant.

The powerful 820 (Camino) chipset will be the AGP 4X host for the most advanced Pentium III CPUs to appear in 1999, the .18mu 133MHz FSB 600+MHz Coppermine parts, and will NOT offer any type of integrated video solution.

For today we're looking at the Intel 810, which according to Intel has been designed to specifically "compliment the Celeron processor". What this means is basically a host of changes to the older 440EX and 440ZX chipsets, including support for the upcoming 100MHz FSB Celerons (beginning with the 500MHz variant of the series in late summer 99) and complete compatibility for the new UltraDMA/66 IDE storage peripheral communication format.

It also means that Intel has reworked the relationship between the aging PCI bus and the memory and I/O controllers towards the reduction of speed-sapping bottlenecks.