This issue of the Private Eye comes from the Intel Developers Forum (IDF for short) in sunny Palm Springs in the California Desert (and at the foot of some really big Mountain). Last week, a chunk of the SE staff scoured the show-floor not only eking out the free food and beverages but also picking up all things bright and Intel. But those of you that think that IDF is only about Intel, grab a cup of coffee, wake up and enjoy the ride. There's a lot to get through, including RAMBUS (it's ALIVE!), a round-up of all things related to the 3D card world, DVD, HDTV and the usual odds, ends and dirt, Hoovered up off of the show-floor.
For those of you unfamiliar with IDF, it happens to be Intel's premier technical forum held semi-annually in Palm Springs. The 150+ sessions and 100 demonstration rooms usually attract 2000 attendees (this year was closer to 3500) mostly made up of IHVs, OEMs, and ISVs. There's usually very little in the way of mainstream press coverage but as we found out this year, that's probably a good thing. The atmosphere and show floor is relatively free of those nasty marketing weasels (sorry but you know how you are!) and more about the nitty gritty mathematical talents of hardcore engineers, double pumped ALUs and Trace Cache.
IDF wouldn't be complete without a few releases from the big I (after all this convention is on their dime). Intel's Chairman, Andrew S. Grove, opened the proceedings by demonstrating a new 1.5GHz chip (that's some 1.5 billion clock cycles/sec) based upon a new 32-bit micro-architecture code-named "Willamette" (pronounced Will-am-et, not Willa-met).
Somewhat closer to reality (in fact by the second half of 2000), Senior VP Albert Yu showed off a 1GHz "Pentium III" (sans the KroyoTech vapor-phase refrigeration this time) emphasizing that Intel has nailed the silicon for a month prior to the show and that the CPU in question was not "just a proliferation of a new design". Dell, Gateway, Compaq et .al will begin sampling 1GHz PIII's by March according to several sources.
Using the same group of engineers that designed the P6, achieving 1Ghz and beyond will be possible via Willamette's new hyper-pipelined design (and on what's thought to be a slightly larger die size), which enables instructions inside the processor to be queued and executed at much faster rates than with the P6 micro-architecture. Intel has rigged the .18micron Willamette with a 20-stage pipeline, which is almost twice that of the P6's 12-stage pipeline (the Athlon has a 10-stage pipeline) and an 'improved' branch prediction unit to compensate for the inevitable impact of a heavily pipelined CPU wasting some of its resources. In addition, Willamette's Trace Cache (an 'advanced' L1 cache) should, in theory, chip in (excuse the pun but I'm a Brit and we make puns where ever possible) to reduce the pipeline bubbles caused by branch mispredictions.