Unlike the Pentium III, which we looked at in March of 1999, the architecture of the Pentium 4 is the product of a serious redesign. Whereas the move from Pentium II to Pentium III added two million transistors, the Pentium 4 sports a whopping 42 million - 14 million more than the currently available Pentium III Coppermine processors. This massive increase in transistor count correlates directly with die size, so naturally, the Pentium 4 is significantly larger than its predecessor. At over 200 square millimeters, it would be a safe bet that this behemoth gets pretty warm as well.

Like all of the other Pentium 4 processors on the market, Intel's 1.7GHz chip is compatible with Socket 423 motherboards. It would be prudent to keep in mind that the next iteration of Intel's socket interface, Socket 478, is around the corner and will not work with Socket 423 processors. If the ability to upgrade is important, keep saving your pennies, because when the next generation of Pentium 4 processors (code named Northwood) is released, they will only be manufactured adhering to the Socket 478 interface.

For the first time since the Pentium Pro, Intel has revamped their micro-architecture; adding features that they say will allow them to deliver leading performance for the next several years. It is important to recognize the significance of this move, since we have not seen a micro-architecture change since the Pentium Pro was released about four years ago.

The first important point to consider is that processor performance is not determined solely by frequency. Rather, it is a function of frequency multiplied by IPC, or instructions per clock cycle. In order to overcome the frequency limitations of the P6 architecture implemented in Pentium II and III systems, Intel increased the number of pipeline stages while decreasing the number of gates per stage, giving the Pentium 4 much needed flexibility. Obviously, Intel is realizing the desired effect, as they were able to debut at 1.5 and have now jumped to 1.7GHz.

Not all things are peachy in the land of the 20-stage pipeline, however. By doubling the depth of the branch prediction pipe, the penalty associated with mis-predictions is greatly increased - rather than flushing 10 speculatively executed instructions, the Pentium 4 has to flush 20, and start the execution over again in the correct program branch. The recovery time on the 20-stage pipe is much longer than the 10-stage pipe, resulting in a lower average number of instructions successfully executed per clock cycle.

To compensate for the lower IPC, Intel has implemented a couple of features that greatly reduce the inherent mis-predict penalty - Execution Trace Cache and the Dynamic Execution Engine.